1. Field of the Invention
The present invention generally relates to microcomputer architectures and, more particularly, is concerned with the use of an asynchronous bus to provide communication between a microprocessor and an independent industry standard synchronous bus.
2. Description of the Prior Art
There are many classifications for computers, ranging from inexpensive microcomputers used in homes and offices, to liquid-cooled supercomputers used in universities and research laboratories. The present invention relates to microcomputers, also known as "personal computers" (or "PCs").
A microcomputer can be defined as a "computer having a mass-produced integrated circuit microprocessor", such as, for example, the Intel 80.times.86 family of products which presently includes the 8086, 80286, 80386 and 80486 microprocessors. Although the microprocessor is the heart and defining feature of a microcomputer, it is not very useful unless it is integrated with a memory and a set of input/output ("I/O") devices, also known as peripherals. These three classes of devices communicate among themselves over a shared set of digital signal lines called a bus.
The bus is logically organized into sets of address, data, and control lines. The address lines are for communicating device addresses which uniquely identify a particular device on the bus. The data lines are for communicating binary data between two bus devices, a bus master, which initiates a data transfer by placing an address on the address lines, and a bus slave, which reads and decodes the address generated by the bus master as its own. The control lines are for coordinating access to the bus and selecting a mode of operation on the bus such as write data or read data modes.
For example, if the bus master is a microprocessor and the bus slave is a memory, the microprocessor may direct the memory to be read by placing the proper logic level on a write/read control line. In this way, the microprocessor gains access to the data stored in the memory location specified by the logic levels placed on the address lines by the microprocessor.
A bus cycle begins when the bus master directs a write or a read on the bus. The bus cycle is completed after all data has been transferred across the bus and the bus master releases control of the bus. If the two devices communicating with each other over the bus operate at the same speed, then a bus cycle may be achieved over a minimum number of clock cycles. If, on the other hand, a bus device can only transmit or receive data over many clock cycles, then a delay must be injected into the state sequencing of the faster device. In such cases, a "ready" control line is typically activated by the slower device to indicate to the faster device that data is available on the bus or has been taken from the bus.
Buses may be generally classified as synchronous or asynchronous, where synchronous buses are distinguished by the requirement that all bus devices synchronize their use of the bus by a single clock source (or a fundamental frequency). An example of a synchronous bus used in a microcomputer is the IBM PC AT I/O Channel, AT-bus or Industry Standard Architecture bus ("ISA-bus"). Present bus frequency standards for the ISA-bus are 8 MHz and 10 MHz.
The ISA-bus, an example of a synchronous bus, is used with the Intel 80386 microprocessor. The ISA-bus provides a 16-bit data bus and a 24-bit address bus. For purposes of this discussion, the control lines of the ISA-bus include four bus cycle definition lines. The bus cycle definition lines define the type of bus cycle being performed. (In the following definitions, and throughout the remainder of this patent document, all signal names that are terminated with an asterisk [*] indicate an active low signal). A bus cycle definition line called memory read ("MEMR*") is active when data is to be read from memory. A bus cycle definition line called memory write ("MEMW*") is active when data is to be written to memory. A bus cycle definition line called I/O read ("IOR*") is active when data is to be read from a peripheral device. A bus cycle definition line called I/O write ("IOW*") is active when data is to be written to a peripheral device.
In addition to the above-mentioned bus cycle definition signals there are some microprocessor specific signals that are used in most microcomputers for specifically interfacing the Intel 80.times.86 microprocessor family. There are two bus control signals and two bus arbitration signals of particular importance for bus interfacing. The bus control signals allow the microprocessor to indicate when a bus cycle has begun, and allows other bus devices to indicate a bus cycle termination. The address status ("ADS*") signal indicates that a valid bus cycle definition, and address, is being driven at the output pins of the 80386 microprocessor. The transfer acknowledge ("READY*") signal indicates that the current bus cycle is complete.
One skilled in the technology will understand the operation of the ISA-bus, other applicable industry standard buses, and the Intel 80.times.86 microprocessor family. At least two references are available on the subject including The IBM PC from the Inside Out, Revised Edition, by Murray Sargent III and Richard L. Shoemaker; and IBM PC AT Technical Reference published by IBM Corporation.
Synchronous buses are ordinarily preferred for microcomputers since they can often transfer data faster than asynchronous buses. Certain applications, however, especially where lengthy communication distances are involved, require asynchronous or "handshake only" type buses. When devices are separated by some distance, the same phase transition of a common clock cannot be guaranteed.
The primary disadvantage of the synchronous ISA-bus has only recently been recognized. Basically, microcomputers are evolving down two separate paths of variables: one set of variables is associated with the bus design and the other set is associated with the microprocessor and memory designs. A synchronous bus, such as the ISA-bus, should remain constant so that microcomputers in a single product line are all compatible. That is, a peripheral such as a modem, printer and so on will operate through a respective controller at the clock frequency defined in the bus specification. Therefore, the bus should only change through more efficient (i.e., cost effective) designs which meet the same specifications. For example, the operating frequency of the bus should remain constant to assure proper operation of all peripherals constructed in accordance with the bus standard.
In contrast, microprocessor and memory technologies are rapidly evolving in functionality and performance. For example, the microprocessor changes in architectural definition (e.g., number of pins, instruction sets, etc.) and clock frequency (e.g., 16 MHz, 25 MHz, 33 MHz), the cache becomes more sophisticated, coprocessors become a part of the microcomputer architecture (e.g., Intel 80387 numeric coprocessor), and main memory becomes faster.
As an example of memory evolution, consider dynamic random access memory, or "DRAM". As DRAM technology improves, the opportunity for improved system performance becomes clear. In the early days of personal computers, the common DRAM chip being used in microcomputers was 64K.times.1 (65,536.times.1 bits), having an access time of 150 nanoseconds. Recently, a standard (i.e., readily available and cost effective) DRAM size used by microcomputer manufacturers was 256K.times.1, having an access time of 100 nanoseconds. Presently, a DRAM chip standard of 1M.times.1 (i.e., 1,048,576.times.1 bits), having an access time of 80 nanoseconds or less is evolving as a commercially feasible standard, and the technology trend is toward a 16M by 1 bit chip.
It is desireable to isolate the memory and microprocessor from the synchronous I/O bus design so that different DRAM and microprocessors at different operating frequencies can be used without affecting the synchronous I/O bus design. Otherwise, if the synchronous bus is not isolated from the computation and storage elements, each technological improvement in memory or microprocessor products will require unique interface circuitry to scale-down communication speed with other devices across the synchronous bus.
Consequently, a need exists for improvements in microcomputer systems to isolate I/O channel design from memory and microprocessor designs.